There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.
High numerical aperture (NA) 193 nanometer (nm) optical projection stepper/scanner systems in combination with advanced photoresist processes now are capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning techniques (DPT) in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch. One such DPT is referred to as litho/etch/litho/etch (LELE), and involves two separate lithographic exposures each followed by an etch process. These exposures are performed using different photomask reticles, each designed to image a portion of the total pattern. However, this scheme includes an additional etch step between lithography steps which increases fabrication cost and adds complexity to process logistics as wafers are transported between lithography and etch areas of a typical fab line. Other DPT processing options include spacer lithography processing often used, for example, in the fabrication of FinFet devices. However, these processes typically introduce several additional steps into a fabrication sequence adding yet further cost and complexity to the overall device fabrication process.
DPT processes which utilize a single etch step known as litho/freeze/litho/etch (LFLE) have also been developed. In LFLE, a first pattern is imaged into a first layer of photoresist, and the resist layer then is “frozen” rendering it unaffected by a second, subsequent photoresist process. A second pattern, complementary to the first pattern, then is formed into the second resist layer. However, the resolution conventionally attainable, for example, for isolated and dense trenches using existing LFLE processes is still limited to that of the lithography process.
Accordingly, it is desirable to provide methods for fabricating semiconductor devices using DPT processes which provide improved resolution over existing DPT processes. Further, it is also desirable to provide methods for designing photomask patterns for such DPT processes. Furthermore, it is also desirable to provide photomasks for such DPT processes. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.